Drechsler, Rolf.
Drechsler, Rolf, 1969-
Rolf Drechsler
VIAF ID: 64793347 ( Personal )
Permalink: http://viaf.org/viaf/64793347
Preferred Forms
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- 100 1 _ ‡a Drechsler, Rolf
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- 100 1 0 ‡a Drechsler, Rolf
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- 100 1 _ ‡a Drechsler, Rolf
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- 100 1 _ ‡a Drechsler, Rolf
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- 100 1 _ ‡a Drechsler, Rolf ‡d 1969-
- 100 1 _ ‡a Drechsler, Rolf ‡d 1969-
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- 100 0 _ ‡a Rolf Drechsler
4xx's: Alternate Name Forms (9)
5xx's: Related Names (2)
Works
Title | Sources |
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Adéquation algorithme architecture automatisée par solveur SMT | |
Advanced BDD Optimization | |
Advanced Formal Verification | |
Advanced Logic Synthesis | |
Applications of Evolutionary Computing : EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings | |
Aspekte der Technischen Informatik : Festschrift zum 60. Geburtstag von Bernd Becker | |
Auf dem Weg zum Quantencomputer Entwurf reversibler Logik ; [studentisches Projekt (QBit)] | |
Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers | |
Automatic Methods for the Refinement of System Models : From the Specification to the Implementation | |
Automatisierte Analyse von virtuellen Prototypen auf der Ebene elektronischer Systeme : Design, Verständnis und Anwendungen | |
Binary decision diagrams : theory and implementation | |
Computer wie funktionieren Smartphone, Tablet & Co.? | |
Debugging at the Electronic System Level | |
Design Automation for Field-coupled Nanotechnologies | |
Design Automation Techniques for Approximation Circuits : Verification, Synthesis and Test | |
Design for Testability, Debug and Reliability : Next Generation Measures Using Formal Techniques | |
Design für Testbarkeit, Fehlersuche und Zuverlässigkeit : Maßnahmen der nächsten Generation unter Verwendung formaler Techniken | |
Dynamic minimization of OKFDDs | |
Enhanced Virtual Prototyping for Heterogeneous Systems | |
Evolutionary algorithms for VLSI CAD, 1998: | |
Exact Design of Digital Microfluidic Biochips | |
Fast FDD based minimization of generalized Reed-Muller forms | |
Formal Modeling and Verification of Cyber-Physical Systems : 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015 | |
Formal Specification Level : Concepts, Methods, and Algorithms | |
genetic algorithm for variable ordering of OBDDs | |
Genetic alogrithms in computer aided design of integrated circuits | |
Graphenbasierte Funktionsdarstellung Boolesche und Pseudo-Boolesche Funktionen | |
In-Memory-Computing : Synthese und Optimierung | |
Information Storage : A Multidisciplinary Perspective | |
Languages, Design Methods, and Tools for Electronic System Design : Selected Contributions from FDL 2015 | |
Local circuit transformations preserving robust path delay fault testability | |
Low power application architecture adaptation using SMT solvers. | |
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen | |
Natural Language Processing for Electronic Design Automation | |
Noch analog oder lebst Du schon? Mit Nœrdman durch die Welt von heute... und morgen | |
On the computational power of ordered Kronecker functional decision diagrams | |
On the relation between BDDs and FDDs | |
On variable ordering and decomposition type choice in OKFDDs | |
Proceedings of the 1st International Workshop on Design, Test and Applications, Dubrovnik, June 8 - 10, 1998. | |
Quality-driven SystemC design | |
Rapid prototyping of fully testable multi level AND, EXOR networks | |
Recent Findings in Boolean Techniques : Selected Papers from the 14th International Workshop on Boolean Problems | |
Research-based Learning in the Context of Smart Environments | |
Reversible and Quantum Circuits : Optimization and Complexity Analysis | |
Robustness and usability in modern design flows | |
Software-Engineering und Hardware-Design eine systematische Einführung | |
Spectral techniques in VLSI CAD | |
Symbolic error metric determination for approximate computing | |
Technische Informatik eine Einführung | |
Test pattern generation using Boolean proof engines | |
Testability of circuits derived from functional decision diagrams | |
Towards a design flow for reversible logic | |
Towards Automated Refinement of TLM Properties to RTL | |
Towards one-pass synthesis | |
Verbessertes virtuelles Prototyping : Mit RISC-V-Fallstudien |