Mateo Valero Cortés
Valero, Mateo
![Sudoc [ABES], France](/viaf/images/flags/SUDOC.png "Sudoc [ABES], France")
Valero Cortés, Mateo
Valero Cortés, Mateo 1952-
Valero, M.
Valero, M. (Mateo)
VIAF ID: 10725577 (Personal)
Permalink: http://viaf.org/viaf/10725577
Preferred Forms
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100 0 _
‡a
Mateo Valero Cortés
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100 1 _ ‡a Valero Cortés, Mateo
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100 1 _ ‡a Valero Cortés, Mateo ‡d (1952- ).
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100 1 _
‡a
Valero Cortés, Mateo
‡d
1952-
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100 1 _
‡a
Valero, M.
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100 1 _ ‡a Valero, M. ‡q (Mateo)
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100 1 _ ‡a Valero, Mateo
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100 1 0
‡a
Valero, Mateo
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100 1 _ ‡a Valero, Mateo
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100 1 _ ‡a Valero, Mateo
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100 1 _
‡a
Valero, Mateo
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100 1 _ ‡a Valero, Mateo
4xx's: Alternate Name Forms (23)
Works
| Title | Sources |
|---|---|
| Acto de investidura del grado de doctor honoris causa Universidad de Zaragoza, 11 de febrero de 2011 |
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| Analysis and architectural support for parallel stateful packet processing |
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| Computadores de altas prestaciones |
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| Comunicaciones por satélite: hacia las redes 3D |
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| Content aware architectures |
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| Contribución al diseño de redes locales de microcomputadores |
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| La Cultura del esfuerzo |
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| Desarrollo del software para un nudo de red local de uC que realice un conmutador de paquetes |
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| Diseño de un sistema de pesaje industrial con célula de carga y microprocesador |
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| Estudio de redes de interconexión con multiplexación adaptativa para sistemas multiprocesadores |
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| Evaluación de arquitecturas vectoriales avanzadas con registros cortos |
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| Exploring coordinated software and hardware support for hardware resource allocation |
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| Heterogeneity-awareness in multihreaded multicore processors |
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| High performance computing : third international symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000 : proceedings |
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| HiPC 2000 |
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| Improving cache behavior in CMP architectures through cache partioning techniques |
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| La Intel·ligència artificial explicada als humans |
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| Internat. Conf. on Appl. Specific Array Processors (5th : 1991 : Barcelona, Sp.). Proceedings of the International Conference ... c1991: |
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| Memory instruction bypassing |
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| Modem acústico para transmisión digital en aplicación a microordenadores |
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| N-dimensional vector instruction set architectures for multimedia applications |
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| Network and Parallel Computing : 15th IFIP WG 10.3 International Conference, NPC 2018, Muroran, Japan, November 29 – December 1, 2018, Proceedings |
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| On mapping selected graph problems onto VLSI array processors |
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| Optimització del rendiment del sistema de memòria en multiprocessadors vectorials |
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| Parallel computing and transputer applications |
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| Particionado y transformación DBT para la resolución de problemas matriciales en procesadores sistólicos |
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| Per-task Energy Accounting in Computing Systems |
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| Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models |
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| Performance Analysis of Sequence Alignment Applications |
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| POSTER |
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| Principios de diseño digital |
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| Procesador de comunicaciones para redes locales con topología multipunto |
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| Profile-guided transaction coalescing—lowering transactional overheads by merging transactions |
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| Protocolo ordenador - N terminales inteligentes |
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| QuakeTM |
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| Quality of service for simultaneous multithreading processors : QoS for SMT processors |
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| Quantifying the Potential Task-Based Dataflow Parallelism in MPI Applications |
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| A Quantitative Analysis of OS Noise |
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| Reducción de conexiones en la organización multiple-bus : estudio general |
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| Reducing fetch architecture complexity using procedure inlining |
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| Register constrained modulo scheduling |
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| Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model |
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| Runahead Threads to improve SMT performance |
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| Runtime-Guided Management of Scratchpad Memories in Multicore Architectures |
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| RVC-based time-predictable faulty caches for safety-critical systems |
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| Scalability of Macroblock-level Parallelism for H.264 Decoding |
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| Sensible Energy Accounting with Abstract Metering for Multicore Systems |
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| Shared queues and arbitration techniques for packet switching multistage interconnection networks |
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| Simulation environment for studying overlap of communication and computation |
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| SMT Malleability in IBM POWER5 and POWER6 Processors |
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| Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation |
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| Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures |
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| Software-Controlled Priority Characterization of POWER5 Processor |
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| Solving matrix problems with no size restriction on a systolic array processor |
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| STM2: A Parallel STM for High Performance Simultaneous Multithreading Systems |
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| Supercomputación : curso |
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| Supercomputing for the Future, Supercomputing from the Past (Keynote) |
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| Supercomputing with commodity CPUs |
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| Swing modulo scheduling : a lifetime-sensitive approach |
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| Taking the heat off transactions: Dynamic selection of pessimistic concurrency control |
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| Task Superscalar: An Out-of-Order Task Pipeline |
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| TERAFLUX: Harnessing dataflow in next generation teradevices |
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| Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core |
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| Thread to Core Assignment in SMT On-Chip Multiprocessors |
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| Throughput Unfairness in Dragonfly Networks under Realistic Traffic Patterns |
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| Toward kilo-instruction processors |
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| Trace-driven simulation of multithreaded applications |
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| Transactional Memory: An Overview |
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| Trends and techniques for energy efficient architectures |
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| Understanding the future of energy-performance trade-off via DVFS in HPC environments |
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| Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory |
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| Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators |
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| Utilization driven power-aware parallel job scheduling |
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| Vector Extensions for Decision Support DBMS Acceleration |
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| Vector multiprocessors with arbitrated memory access |
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| Vectorized AES Core for High-throughput Secure Environments |
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| Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications |
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| WormBench |
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| মুখবন্ধ |
|
