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Wunderlich, Hans-Joachim National Library of the Netherlands National Library of Israel NII (Japan) German National Library ISNI Library of Congress/NACO BIBSYS

VIAF ID: 101074629 (Personal)

Permalink: http://viaf.org/viaf/101074629

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Title Sources
analytical approach to the partial scan problem German National Library
Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen German National Library
Automatisierung des Entwurfs vollständig testbarer Schaltungen German National Library
common approach to test generation and hardware verification based on temporal logic German National Library
Configuring flip-flops to BIST registers German National Library
Design automation of random testable circuits German National Library
effectiveness of different test sets for PLAs German National Library
Efficient test set evaluation German National Library
Emulation of scan paths in sequential circuit synthesis German National Library
Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen German National Library
Generating pseudo-exhaustive vectors for external testing German National Library
HIST - Hierarchischer Selbsttest German National Library
Hochintegrierte Schaltungen prüfgerechter Entwurf und Test ; mit 52 Tabellen German National Library
Integrated tools for automatic design for testability German National Library
integration of test and high level synthesis in a general design environment German National Library
Maximizing the fault coverage in complex circuits by minimal number of signatures German National Library
Methoden der Testvorbereitung zum IC-Entwurf German National Library
Models in hardware testing : lecture notes of the forum in honor of Christian Landrault National Library of the Netherlands Library of Congress/NACO
Multiple distributions for biased random test patterns German National Library
On computing optimized input probabilities for random tests German National Library
On fault modeling for dynamic MOS circuits German National Library
Optimized synthesis techniques for testable sequential circuits German National Library
Parametrisierte Speicherzellen zur Unterstützung des Selbsttests mit optimierten und konventionellen Zufallsmustern German National Library
Probabilistische Verfahren für den Test hochintegrierter Schaltungen. - German National Library Library of Congress/NACO National Library of Israel National Library of the Netherlands BIBSYS
Protest: a tool for probabilistic testability analysis German National Library
pseudo-exhaustive test of sequential circuits German National Library
random pattern testability of programmable logic arrays German National Library
Self test using unequiprobable random patterns German National Library
Signature analysis and test scheduling for self-testable circuits German National Library
Simulation results of an efficient defect analysis procedure German National Library
Steigerung der Effizienz beim Test mit Zufallsmustern German National Library
synthesis approach to reduce scan design overhead German National Library
synthesis of self-test control logic German National Library
TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control German National Library
Time-optimal control policies for cascaded production-inventory systems with control and state constraints German National Library
Tools and devices supporting the pseudo-exhaustive test German National Library
unified approach for the synthesis of self-testable finite state machines German National Library
unified method for assembling global test schedules German National Library
Zur statistischen Analyse der Testbarkeit digitaler Schaltungen German National Library
Zuverlässigkeit und Entwurf : 5. GI/GMM/ITG-Fachtagung vom 27. bis. 29. September 2011 in Hamburg-Harburg Library of Congress/NACO

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Open Section Close Section History of VIAF ID:101074629 (9)