Biere, Armin, 1967-....
Biere, Armin.
Armin Biere
VIAF ID: 45040007 ( Personal )
Permalink: http://viaf.org/viaf/45040007
Preferred Forms
- 100 0 _ ‡a Armin Biere
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- 100 1 _ ‡a Biere, Armin
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- 100 1 _ ‡a Biere, Armin
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- 100 1 _ ‡a Biere, Armin ‡d 1967-
- 100 1 _ ‡a Biere, Armin ‡d 1967-
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- 100 1 _ ‡a Biere, Armin, ‡d 1967-....
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4xx's: Alternate Name Forms (9)
5xx's: Related Names (5)
- 510 2 _ ‡a Albert-Ludwigs-Universität Freiburg ‡4 affi ‡4 https://d-nb.info/standards/elementset/gnd#affiliation ‡e Affiliation
- 510 2 _ ‡a Johannes Kepler Universität Linz ‡4 affi ‡4 https://d-nb.info/standards/elementset/gnd#affiliation ‡e Affiliation
- 510 2 _ ‡a Universität Karlsruhe
- 510 2 _ ‡a Universität Linz
- 551 _ _ ‡a Villingen im Schwarzwald ‡4 ortg ‡4 https://d-nb.info/standards/elementset/gnd#placeOfBirth
Works
Title | Sources |
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case study on different modelling approaches based on model checking verifying numerous versions of the alternating bit protocol with SMV | |
CAV 2014 | |
Clausal proofs for pseudo-boolean reasoning | |
Combining local and global model checking | |
Compressing BMC encodings with QBF | |
Computer Aided Verification : 26th International Conference, CAV 2014, Held as Part of the Vienna Summer of Logic, VSL 2014, Vienna, Austria, July 18-22, 2014, Proceedings | |
Digitaltechnik - eine praxisnahe Einführung | |
Efficient All-UIP learned clause minimization | |
Efficiently representing existential dependency sets for expansion-based QBF solvers | |
Effiziente Modellprüfung des [my-Kalküls] mit binären Entscheidungsdiagrammen | |
Encodage Efficace des Systèmes Critiques pour la Vérificaton Formelle par Model Checking à base de Solveurs SAT | |
Encoding Redundancy for Satisfaction-Driven Clause Learning | |
Formal methods group ETH Zürich | |
Handbook of satisfiability | |
Hardware and software: verification and testing revised selected papers | |
HVC 2012 | |
Improving AMulet2 for verifying multiplier circuits using SAT solving and computer algebra | |
Incremental column-wise verification of arithmetic circuits using computer algebra | |
JVM independent replay in java | |
Liveness checking as safety checking for infinite state spaces | |
Local redundancy in SAT: generalizations of blocked clauses | |
MBMV 2023 Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen : 26. Workshop, 23.-24. März 2023 in Freiburg | |
Mining definitions in Kissat with Kittens | |
Non-clausal redundancy properties | |
On safety verification using PDR and Reverse PDR | |
Propagation based local search for bit-precise reasoning | |
SAT 2006 | |
SAT solving with GPU accelerated inprocessing | |
Strong Extension-Free Proof Systems | |
Subroutine inlining and bytecode abstraction to simplify static and dynamic analysis | |
Theory and applications of satisfiability testing -- SAT 2006 : 9th international conference, Seattle, WA, USA, August 12-15, 2006 : proceedings | |
Tools and algorithms for the construction and analysis of systems : 26th International Conference, TACAS 2020, held as part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2020, Dublin, Ireland, April 25-30, 2020, proceedings, Part II | |
VSL 2014 |