Wanhammar, Lars.
Wanhammar, Lars, 1944-
Lars Wanhammar
VIAF ID: 60731959 (Personal)
Permalink: http://viaf.org/viaf/60731959
Preferred Forms
- 100 0 _ ‡a Lars Wanhammar
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- 100 1 _ ‡a Wanhammar, Lars
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- 100 | _ ‡a Wanhammar, Lars
- 100 1 _ ‡a Wanhammar, Lars
- 100 1 0 ‡a Wanhammar, Lars
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- 100 1 _ ‡a Wanhammar, Lars ‡d 1944-
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- 100 1 _ ‡a Wanhammar, Lars, ‡d 1944-
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4xx's: Alternate Name Forms (12)
5xx's: Related Names (3)
- 551 _ _ ‡a Linköping ‡4 ortw ‡4 https://d-nb.info/standards/elementset/gnd#placeOfActivity
- 510 2 _ ‡a Linköpings Universitet ‡4 affi ‡4 https://d-nb.info/standards/elementset/gnd#affiliation ‡e Affiliation
- 551 _ _ ‡a Vansbro ‡4 ortg ‡4 https://d-nb.info/standards/elementset/gnd#placeOfBirth
Works
Title | Sources |
---|---|
Analog filters using MATLAB | |
Arithmetic | |
Bit-serial VLSI design of decimation comb filters for oversampling A/D converters | |
A complex multiplier using overturned-stairs adder tree | |
Design and implementation of an inverse quantizer for the MPEG-2 standard | |
Design of an 128-point FFT processor for OFDM applications | |
A design platform for computer-aided design of analog amplifiers | |
A digital down converter for a wideband radar receiver | |
Digital filters, 2002: | |
Digital Hilbert transformers composed of identical allpass subfilters | |
Directions in embedding of DSP functionalities. | |
DSP integrated circuits | |
Efficient radix-4 and radix-8 butterfly elements | |
Elektriska filter | |
Filter structures composed of allpass and fir filters for interpolation and decimation with factors of two | |
High-speed recursive filtering using the frequency-response masking approach | |
Implementation of a combined interpolator and decimator for an OFDM system demonstrator | |
Implementation of a fast MPEG-2 compliant Huffman decoder | |
Implementation of maximally fast ladder wave digital filters using a numerically equivalent state-space represenation | |
Implementation of static DSP algorithms using multiplexed PE:s | |
Low-power design with synthesis tools | |
Maximally fast scheduling of bit-serial lattice wave digital filters using three-port adaptor allpass sections. | |
An MILP approach for the design of linear-phase FIR filters with minimum number of signed-power-of-two terms | |
Minimum-adder integer multipliers using carry-save adders | |
An MPEG-2 video decoder DSP architecture | |
Narrow-band and wide-band single filter frequency masking FIR filters | |
New approaches to high speed Huffman decoding | |
On implementation of fast, bit-serial loops | |
On the frequency response of M-channel mixed analog and digital maximally decimated filter banks | |
Optimization-based design space exploration of analog circuits | |
Parallel processing in industrial real-time applications, c1992: | |
Port controllers for a GALS implementation of a 2-D DCT processor | |
Port controllers for GALS with first come first served function | |
A power-saving technique for bit-serial DSP ASICs | |
A radix-r FFT/IFFT architecture with distributed control unit | |
A robust differential logic style with NMOS logic nets | |
Serial squarers and serial/serial multipliers | |
Structural and algorithmic description | |
Switching activity in bit-serial constant-coefficient serial/parallel multipliers | |
System design with Mentor Graphics' tool | |
Tidsdiskreta filter | |
Tuning and compensation of temperature effects in analog integrated filters | |
Use of computer simulations in ASIC system design | |
Using optimization to find design trade-offs in analog amplifier design | |
VHDL code generator for a complex multiplier | |
Vol. 2. | |
Wave digital filter structures for high-speed narrow-band and wide-band filtering. | |
Word length estimation for memory efficient pipeline FFT/IFFT processors | |
Yield enhancement techniques in analog design automation |