Reis, Ricardo A. L. (Ricardo Augusto da Luz)
Reis, Ricardo, 19..-...., ingénieur
Reis, Ricardo
Reis, Ricardo, 1978-
Reis, Ricardo A.
Reis, Ricardo Augusto da Luz
VIAF ID: 265160001826530300009 ( Personal )
Permalink: http://viaf.org/viaf/265160001826530300009
Preferred Forms
- 200 _ | ‡a Reis ‡b Ricardo Augusto da Luz
- 100 1 _ ‡a Reis, Ricardo
- 100 1 _ ‡a Reis, Ricardo
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- 100 1 _ ‡a Reis, Ricardo A. L. ‡q (Ricardo Augusto da Luz)
- 100 1 _ ‡a Reis, Ricardo A. L. ‡q (Ricardo Augusto da Luz)
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- 100 1 _ ‡a Reis, Ricardo ‡d 1978-
- 100 1 _ ‡a Reis, Ricardo, ‡d 19..-...., ‡c ingénieur
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4xx's: Alternate Name Forms (11)
Works
Title | Sources |
---|---|
15th Symposium on Integrated Circuits and Systems Design, c2002: | |
Anais | |
Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. | |
Circuit Design for Reliability | |
Design of system on a chip : devices & components | |
Design, optimization and integration of Doherty power amplifier for 3G/4G mobile communications | |
Electromigration Inside Logic Cells : Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS | |
Élégies. | |
Fault-tolerance techniques for SRAM-based FPGAs | |
Informatics curricula and teaching methods : IFIP TC3/WG3.2 Conference on Informatics Curricula, Teaching Methods, and Best Practice (ICTEM 2002), July 10-12, 2002, Florianópolis, SC, Brazil | |
Information technology selected tutorials | |
Memory circuit hardening to Multiple-Cell Upsets | |
Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs | |
Poesia | |
Protecting Chips Against Hold Time Violations Due to Variability | |
Radiation effects on embedded systems | |
SBCCI 2000 | |
Sociedade Brasileira de Computação. Congresso (5th : 1985 : Porto Alegre, Brazil). Anais, 1985?: | |
Soft Error Reliability Using Virtual Platforms : Early Evaluation of Multicore Systems | |
Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique | |
A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate. | |
TESS : évaluateur topologique prédictif pour la génération automatique des plans de masse de circuits VLSI | |
Transient-fault robust systems exploiting quasi-delay insensitive asynchronous circuits. | |
Transistor Level Automatic Generation of Radiation-Hardened Circuits. | |
Vlsi-Soc: From Systems To Silicon : Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia. | |
VLSI-SoC: Technology Advancement on SoC Design : 29th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2021, Singapore, October 4–8, 2021, Revised and Extended Selected Papers |