Bellido, Manuel J., 1964-....
Bellido, Manuel J.
VIAF ID: 279638144 ( Personal )
Permalink: http://viaf.org/viaf/279638144
Preferred Forms
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- 100 1 _ ‡a Bellido, Manuel J. ‡d 1964-
- 100 1 _ ‡a Bellido, Manuel J. ‡d 1964-
- 100 1 _ ‡a Bellido, Manuel J., ‡d 1964-
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- 100 1 _ ‡a Bellido, Manuel J., ‡d 1964-....
Works
Title | Sources |
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Integrated Circuit Design : Power and Timing Modeling, Optimization and Simulation : 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002 : Proceedings | |
Logic-timing simulation and the degradation delay model |